ADSP-21266SKBCZ-2C

Product Summary

The ADSP-21266SKBCZ-2C is a member of the SIMD SHARC family of DSPs featuring Analog Devices Super Harvard Architecture. The ADSP-21266SKBCZ-2C is source code compatible with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. Like other SHARC DSPs, the ADSP-21266SKBCZ-2C is a 32-bit/40-bit floating-point processor optimized for high performance audio applications with its dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface.

Parametrics

ADSP-21266SKBCZ-2C absolute maximum ratings: (1)Internal (Core) Supply Voltage (VDDINT):–0.3 V to +1.4 V; (2)Analog (PLL) Supply Voltage (AVDD): –0.3 V to +1.4 V; (3)External (I/O) Supply Voltage (VDDEXT):–0.3 V to +3.8 V; (4)Input Voltage: –0.5 V to VDDEXT +0.5 V.

Features

ADSP-21266SKBCZ-2C features: (1)Access to asynchronous external memory; (2)16 multiplexed address/data lines that can support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data; (3)66M byte/sec transfer rate for 200 MHz core rate; (4)50M byte/sec transfer rate for 150 MHz core rate; (5)256 word page boundaries; (6)External memory access in a dedicated DMA channel; (7)8- to 32-bit and 16- to 32-bit word packing options; (8)Programmable wait state options: 2 to 31 CCLKs; (9)Serial peripheral interface (SPI); (10)Master or slave serial boot through SPI; (11)Full-duplex operation; (12)Master-slave mode multimaster support; (13)Open-drain outputs; (14)Programmable baud rates, clock polarities, and phases; (15)3 muxed flag/IRQ lines; (16)1 muxed flag/timer expired line; (17)JTAG access to memory permitted with a 64-bit key; (18)Protected memory regions that can be assigned to limit access under program control to sensitive code; (19)PLL has a wide variety of software and hardware multiplier/divider ratios.

Diagrams